// Sample Verilog — samplefiles.com
// An 8-bit up-counter with synchronous reset and enable, plus a small testbench.
`timescale 1ns / 1ps

module counter #(parameter WIDTH = 8) (
    input  wire             clk,
    input  wire             rst,
    input  wire             en,
    output reg  [WIDTH-1:0] count,
    output wire             overflow
);
    assign overflow = en && (count == {WIDTH{1'b1}});

    always @(posedge clk) begin
        if (rst)
            count <= {WIDTH{1'b0}};
        else if (en)
            count <= count + 1'b1;
    end
endmodule

module counter_tb;
    reg clk = 0, rst = 1, en = 0;
    wire [7:0] count;
    wire overflow;

    counter #(.WIDTH(8)) dut (.clk(clk), .rst(rst), .en(en), .count(count), .overflow(overflow));

    always #5 clk = ~clk;

    initial begin
        $dumpfile("counter.vcd");
        $dumpvars(0, counter_tb);
        #12 rst = 0; en = 1;
        #100 $display("count = %0d", count);
        $finish;
    end
endmodule